Gaurav Kamalkar
Clocking | Physical Design
- Role
- Senior Physical Design Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Gaurav Kamalkar
Skilled in Cadence Spectre, C, Proteus, VHDL, and Cadence Virtuoso. Strong education professional with a Master of Technology focused in Integrated Electronics and Circuits from Indian Institute of Technology, Delhi.
Experience
Senior Physical Design Engineer
Jun 2025 — Present · Bengaluru, IN
Circuit simulations - Variation, dcd, jitter impact on clock circuits. 4Ghz block convergence GAA,FinFet technology node device studies Custom clocking solutions for reticle size AiSoC. Used AI tools to develope advanced flows for custom clocking solutions designs. PLL, GPIO integration. Multivoltage design pnr convergence.
Education
Hanumantrao Chate JR. College of Science, Kolhapur
High School
2010 — 2012
Indian Institute of Technology, Delhi
Master of Technology, Integrated Electronics and Circuits
2017 — 2019
Savitribai Phule Pune University
Bachelor's degree, Electronics and Telecommunication Engineering
2012 — 2016
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