Gaurav Yadav

About Gaurav Yadav

10.5 years of Micro-architecture Design and RTL Implementation experience on IPs like Database Query acceleration, PCIe End Point, Interlaken, and HMCCSkills• System Verilog, Verilog, Python, Tcl, Perl, C and C++• FPGA- High speed design – Static Timing Analysis and closure, Clock Domain Crossing- Optimal design choices and floor planning for > 90% area utilization with up to 8 logic levels- Building and maintaining IP libraries.• PCIe data and transaction layer expertise.• Tools- Expertise: Xilinx Vivado, Intel Quartus Prime, Synopsys- VCS, DVE- Working knowledge: Synopsys Design Compiler, PrimeTime, Cadence ncsim, Mentor modelsim, Spyglass.• FPGAs: AWS Custom metal server, Intel Stratix10, Arria10, StratixV, Xilinx Spartan6, NetFPGA-1G

Experience

1. Senior Soc Design Engineer

   Amazon Lab126

   Jul 2023 — Present · Sunnyvale, CA, US

   Owned and delivered the top-level System on Chip (SoC), coordinating integration across multiple partitions and sub-systems.• Upgraded workflows for design integration, re-wrote the existing TCL-based flow to generate the top-level design.• Unblocked and facilitated collaboration between verification and backend physical design (PD) teams, resolving conflicts to ensure timely delivery of the top-level design.• Collaborated closely with the PD team to optimize chip design, minimizing chip area through multiple iterations and strategic subsystem placements.• Worked with the platform team to incorporate pinout position requests and implemented feedback on chip design.• Owned and updated the Debug subsystem from previous chips, optimizing functionality and streamlining unused features in collaboration with software teams.• Collaborated with third-party vendors to refine SD card IPs, coordinating multiple meetings and facilitating communication between verification teams and vendors.• Acted as a subject matter expert for the clock and reset block, providing training and guidance to a junior team member for updates based on new chip requirements.

Education

• Savitribai Phule Pune University

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2008 — 2011

• University of Southern California

  Master of Science (MS), Digital VLSI

  2012 — 2014

Skills

• Computer Architecture
• C
• Model Sim
• Fpga
• Vlsi
• Vhdl
• Signal Processing
• Simulink
• Spice
• Cadence Virtuoso Layout
• Perl
• Embedded Systems
• C++
• Microcontrollers
• Html
• Java
• Sql
• Linux
• Modelsim
• Perl Script
• Verilog
• Pspice
• C#
• Xilinx Ise
• Xilinx
• Cadence Virtuoso
• Matlab
• Tcl