Gaurav Shahdadpuri
Senior Design Engineer @恩智浦半导体
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WORK HISTORY
Senior Design Engineer @恩智浦半导体
EDUCATION
Dr. Virendra Swaroop Memorial Pubilc School
12, Science
INDERAPRASTHA ENGINEERING COLLEGE, GHAZIABAD
BTech - Bachelor of Technology, Electrical, Electronics and Communications Engineering
Pine Training Academy
Full Custom Asic Design and Layout
Inderprastha Engineering College
Bachelor's degree, Electronics and Communications Engineering
ABOUT GAURAV SHAHDADPURI
Analog verification of various IP by building functional testbench patterns in SV,UVM and C Experienced with DFT Safe stating of all analog IP’s and brought changes in IP’sExposure to creating UPF testbenches and Low Power Checks. Exposure to clocking, reset and power architecture Experience in Spice simulation using Spectre, hspice. Good understanding of Spectre/hspice models and checks /asserts Virtuoso Analog Design Environment: ADE L/XL/GXL, ADE Explorer/Assembler Basic understanding of DFM, DRC, Parasitic Extraction, Reliability and post layout simulation Experience in doing mixed signal simulation using AMS Designer. Working knowledge of Languages: Skill, OCEAN, Spectre MDL, VerilogA, VerilogAMS, Verilog System Verilog Good exposure to Behavior modelling and Real number modelling. Exposure to SV assertions Exposure to performing statistical analysis, optimization and corner analysis. Proficient in UNIX Shell Scripting, TCL, OCEAN and SKILL language. Experience in EMIR flow (electro-migration and IR drop analysis)
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