Gaurav Saini

About Gaurav Saini

I am Gaurav Saini and have 10 years of experience in Physical design and Static Timing Analysis. Along with PD and STA, I have also worked on Synthesis, Constraints Generation & validation activities. I have done 3 tapeouts on 16 nm and multiple tapeouts on 28nm, 45 nm, 65nm and 90 nm technologies. I have worked with different clients – US, Japan and interacted with teams available at different time zones. I have been to US (Fremont, CA) for 6 weeks for the kickstart of a project. I can explore my ability with following skills and tools.Technical Skills:Physical Synthesis/Place/Route: Encounter (Cadence) – Block level and top level design implementation ICCompiler (Synopsys)- Block level implementation Olympus-SoC (Mentor) – For hierarchical flows, and Correlation activities with PT.Static Timing Analysis: Prime Time/SISynthesis: Design CompilerRC Extraction: Star RCXTPhysical Verification: Calibre DRC/LVSFormal Verification: Formality (Synopsys)Scripting Languages: TCL, perl, shellStatus Reporting: Pinpoint Other tools: Spyglass-TxV, Conformal-LEC, GCAApplication Packages MS-office (Word, Power Point, Excel)

Experience

1. Sr Physical Design Engineer

   NVIDIA

   Jul 2017 — Present · San Francisco, CA, US

   Working as a PD Engineer

Education

• Maharshi Dayanand University

  B.Tech, Electronics and Instrumentation Control

  2003 — 2007

Skills

• Place & Route
• Soc
• Compilers
• Logic Synthesis
• Clock Tree Synthesis
• Vhdl
• Microelectronics
• Asic
• Formal Verification
• Vlsi
• Physical Design
• Synopsys Primetime
• Static Timing Analysis
• Perl
• Verilog
• Rtl Design
• Floorplanning
• Tcl