Gaurav Raj

About Gaurav Raj

Self-motivated and Detail-Oriented Design Engineer at Qualcomm, specializing in Design-Technology Co-Optimization (DTCO) to drive innovation across advanced process nodes. Proven expertise in Device and Process Integration, Design Enablement, and Technology Development for High-Performance, Scalable SOCs. Strong foundation in Semiconductor Physics, Yield Enhancement, and PPA (Power, Performance, Area) optimization. Adept at bridging Design and Process teams to align Technology capabilities with Product Goals, enabling efficient and robust Silicon solutions.

Experience

1. Senior Physical Design Engineer

   Qualcomm

   Mar 2025 — Present · Bengaluru, IN

   Defining and Tracking PPA Goals across Design Cycles.• Collaborating with Architecture, RTL, and Physical Design teams to drive efficient implementation.• Driving DTCO (Design Technology Co-Optimization) initiatives with Foundry and EDA Partners.• Performing Block-Level Physical Design Regressions to validate PPA Boosters.• Performing workload-based Power and Performance Modeling.• Supporting Post-Silicon Validation and correlation with Pre-Silicon Models.• Evaluating and Optimizing Standard-Cell Architectures for PPA improvements.• Exploring 3DIC and STCO (System Technology Co-Optimization) strategies for Next-Gen Designs.

Education

• National Institute of Technology Delhi

  M.Tech, Electronics and Communications Engineering

• Chandrasheel Vidyapeeth, Muzaffarpur

  Secondary School

• St. Joseph Senior Senior Seconady School Muzaffarpur

  Higher Secondary School

• MIT Pune

  B.Tech, Electronics and Communications Engineering

  2014 — 2018