Gaurav Pratap Singh
Principal Engineer @Renesas Electronics
New Delhi, DL, IN
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Dec 2024 — Present
Principal Engineer @Renesas Electronics
View department →
Noida, IN
EDUCATION
2006 — 2009
ITM Gurgaon (MDU University)
B.E
2009 — 2010
CDAC Pune
P.G. Diploma
2003 — 2006
Government Polytechnic
Diploma
SKILLS
Rtl DesignXilinxRtl CodingVerilogModelsimVhdlPcieAlteraFpgaAlgorithms
ABOUT GAURAV PRATAP SINGH
RTL Design Engineer | ASIC/SOC Implementation Experienced RTL Design Engineer with over 12 years of expertise in ASIC and SOC implementation. Proven track record in micro-architecture definition, RTL development, and hardware debugging on FPGA platforms. Skilled in VHDL, Verilog, CDC Spyglass, and Linting. Currently contributing to Smart NIC solutions at Xilinx Inc (Acquired by AMD). Recognized with multiple awards for excellence in design and impact.
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.