Gaurav Lalani
Senior Staff Digital Design Engineer | ASIC | CPU & Peripheral Subsystems | Low Power Architecture | RTL & Silicon Debug | 10+ Years Experience
- Role
- Senior Staff Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Gaurav Lalani
Experienced ASIC Digital Design Engineer with more than decade of hands-on expertise in IP and subsystem design across diverse cores and applications. Proven track record in front-end RTL development, low-power architecture, and silicon lifecycle—from concept to debug.Skilled in collaborating across architecture, verification, and implementation teams to deliver high-quality designs with optimized power and performance. Passionate about solving complex design challenges and contributing to next-gen product innovations.Looking to make meaningful impact in dynamic, technology-driven environments that value quality, ownership, and cross-functional collaboration.
Experience
Senior Staff Engineer
Dec 2025 — Present
Education
Nirma University
Master of Technology (M.Tech.), VLSI Design
2012 — 2014
Skills
- Digital Designs
- Verilog
- Rtl Design
- System Verillog
- Logic Synthesis
- Vlsi
- Static Timing Analysis
- Soc
- Debugging
- Gate Level Simulation
- Rtl Verification
- Semiconductors
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