Gaurav Gupta

About Gaurav Gupta

18 Years of Mixed-Signal Circuit Design Experience, Presently working as Associate Director for PLLs and Analog IPs in FinFet nodes in Samsung, 5 Years as Architecture and Team Lead in Intel, 10 years with Analog Devices- Architect, System and Circuit Design Lead of High Bandwidth Memory - Eye Margin Analysis, Post Silicon Debug, LDO, DLLs, Clocking, Slicer Design, Power Delivery, Floorplanning, Timing Libs, Behavioral Modelling, Mixed Signal Validation- Successful First Silicon experience on 8-10 different Silicon (including FinFets) with Tight Deadlines- Design Lead of Multiphase DC-DC Buck Converter with Digital Control Loop - High Speed SAR ADC, Accurate DACs, Control Loop, Digital PWM, Power FETs, MiM Cap, ESD - successful Silicon and post-Si debug experience- Precision Pipeline SAR ADCs, Flash ADC inside CT Sigma Delta Loop - High Performance Crystal Oscillators, DLL, Relaxation Oscillators - went into successful product- Ultra Low Noise Reference and Reference Buffer, Temperature Sensors, High Voltage DAC Buffer - Mixed Signal Verification of Complex Integrated ASSPs- Architecture, Specification Definition, Layout Floor planning, Design-Verification, Reviewing Silicon Data and Debug

Experience

1. Principal Analog Engineer

   Renesas Electronics

   Apr 2025 — Present · Bengaluru, IN

   PMIC, Battery Chargers

Education

• Indian Institute of Technology, Bombay

  M.Tech., Microelectronics

  2004 — 2006

• Stanford University

  SCPD - Non Degree , Analog Digital Interface Circuits by Prof. Boris Murmann

• Aligarh Muslim University

  B.Tech., Electronics and Communications

  1999 — 2003

Skills

• Verilog
• Vlsi
• Mixed Signal
• Ic
• Cmos
• Semiconductors
• Asic
• Analog
• Eda
• Physical Design
• Soc