Garv Kumar Sharma

About Garv Kumar Sharma

I’m an aspiring VLSI Engineer with a strong focus on Analog and Digital IC Design, passionate about building efficient and reliable semiconductor circuits.I have hands-on experience in Cadence Virtuoso, Xilinx Vivado, and EDA Playground, covering the complete design flow — from schematic and layout to post-layout simulation and verification. My work includes designing radiation-hardened SRAM cells, analog amplifiers, ring oscillators, and digital logic circuits using 45nm–180nm technologies.I’ve interned at IIT Jammu (Analog IC Design) and Entuple Technologies (Physical Design & Verification), gaining real-world exposure to industry-standard EDA tools and design methodologies.Beyond technical work, I’ve led as Chair of MTT-S Student Chapter and Program Representative, fostering teamwork, communication, and leadership within the VLSI community.I’m driven to contribute to the semiconductor design ecosystem, with interests in Analog/Mixed-Signal Design, Physical Verification, and Custom Layout Design.Let’s connect to collaborate on VLSI design, innovation, or semiconductor R&D opportunities.

Experience

1. Program Representative

   Vit-Ap University

   Nov 2023 — Present

   Gate Qualified in 2nd Year of B Tech. Selection Criteria: 1. Highest CGPA.Responsibilities:1. Representing my programme batch students in the meetings. To have collective feedback and suggestions from my student friends. To attend the PR meetings of the university

Education

• VIT-AP University

  Bachelor of Technology - BTech, Electronic and Communications Engineering Technology

• DPS World School

  Class 12th

• DPS World School

  Class 10th