Gangadas Ns

About Gangadas Ns

I am a dedicated Design Verification Engineer with hands on experience in SoC and IP evel functional verification, pre silicon validation, and performance analysis. My work focuses on ensuring functional correctness, reliability, and performance of complex digital systems through a structured and methodical verification approach.Skilled in SystemVerilog, UVM, and SVA, I specialize in testbench architecture design, coverage driven verification, and assertion-based verification (ABV). I have worked extensively on AXI, AHB, APB, I2C, and SPI protocols, building scalable UVM environments and achieving full functional and code coverage.I’m proficient in using industry standard tools like Synopsys VCS, QuestaSim, Verdi for simulation, debugging, and waveform analysis. I’ve actively contributed to multiple verification cycles involving test plan creation, RTL debugging, coverage closure, and signoff validation, ensuring the design meets performance and functional goals.Known for my attention to detail, adaptability, and problem solving mindset, I’m passionate about bridging design intent with verification strategy. My goal is to continuously evolve as an engineer contributing to the development of reliable, high quality silicon and driving innovation through disciplined verification practices.Let’s connect if you’re involved in SoC design, verification, or emulation always open to learning, sharing ideas, and collaborating on cutting edge projects in the semiconductor world.

Experience

1. Design Verification Engineer

   Tech Mahindra

   Jun 2024 — Present · Kochi, IN

Education

• Cochin University of Science and Technology

  Bachelor of Technology - BTech