Ganessh Balaji Chandrasekaran
SOC RTL Lead, DDG, Intel Corporation
- Role
- Soc Rtl Lead, Ddg at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Ganessh Balaji Chandrasekaran
Working as a SOC RTL Design Engineer for last couple of years after starting the Intel career as Physical Design Engineer. Completed 3 tapeouts as RTL Design Engineer and 2 tapeouts as Physical Design Engineer. Experienced in complete product development life cycle through FE/BE design, verification & testing. Driven by project success and success of the team.
Experience
Soc Rtl Lead, Ddg
Jan 2025 — Present
Education
University of Southern California
Master of Science, Electrical Engineering
2009 — 2011
GRG Matriculation Higher Secondary School, Coimbatore
XII Higher, Secondary
1989 — 2003
PSG College of Technology
Bachelor of Engineering (BE), ECE
2003 — 2007
Skills
- Logic Synthesis
- Synopsys Primetime
- Cadence Virtuoso
- C
- Cdc
- Vlsi
- Soc
- Primetime
- Debugging
- Low-Power Design
- Arm
- Perl Script
- Verilog
- Formal Verification
- System on a Chip (Soc)
- Modelsim
- Clocking
- Systemverilog
- Cadence
- Cmos
- Arm 9
- Analog
- Perl
- Arm9
- Rtl Design
- Digital Signal Processors
- Spyglass
- C++
- Integrated Circuit Design
- Static Timing Analysis
- Digital Electronics
- Synopsys Tools
- Vhdl
- Lint
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