Ganesh Prabhu

About Ganesh Prabhu

Expertise in defining methodologies and flow automation for Synthesis / P&R / Timing Analysis / Power Analysis / Physical Verification / SoC prototyping and partitioning / Low Power designs / DFT insertion / Pre & Post mask functional ECOs.Involved in IP qualification and benchmarking in different technology nodes.Experience as a Consultant and Application Engineer for EDA tools used for RTL / netlist debugging, functional qualification, timing exception creation and verification.Proficient with Verilog, VHDL, TCL, Perl, Shell, Digital Design flows

Experience

1. Deputy Director

   GlobalFoundries

   Mar 2025 — Present

Education

• Shanmugha Arts, Science, Technology and Research Academy

  Bachelor of Engineering (B.E.), Electronics and Instrumentation Engineering

  1997 — 2001

• Indian Institute of Management, Calcutta

  EPBM

  2007 — 2007

Skills

• Integrated Circuit Design
• Physical Design
• Application-Specific Integrated Circuits (Asic)
• Vhdl
• Perl
• Eda
• Low-Power Design
• Formal Verification
• Timing Closure
• Clock Tree Synthesis
• System on a Chip (Soc)
• Primetime
• Static Timing Analysis
• Cadence
• Ic
• Ncsim
• Dft
• Verilog
• Tcl
• Functional Verification
• Debugging
• Logic Synthesis
• Rtl Coding
• Systemverilog
• Vlsi
• Soc
• Rtl Design
• Fpga
• Asic
• Semiconductors