Ganesh Dhole

About Ganesh Dhole

Experienced professional of ASIC SoC Physical Design & Foundational Digital IP development (PHY/SERDES/Sensors). Worked on 4/5/7/10/14nm node (Samsung/Intel/TSMC).Experience in Block level Physical design - floorplanning, Placement, CTS, route, ECO implementation and signoff checks with Industry standard Tools(Innovus & ICC2). Good experience in deep sub-micron technology issues like Power analysis, Voltage Drop (IR drop) Analysis & Electro-migration (EM) etc. Very good analytical skills across domainsSound knowledge of tcl & CMOS Technologies, fast ramp up speed in projects.Managed critical deliveries with fast turn-around times. Ability and flair to acquaint with diversified business environments.

Experience

1. Principal Design Engineer

   Cadence

   Jan 2026 — Present · Pune, IN

Education

• Doctor Babasaheb Ambedkar Marathwada University

  Bachelor of Engineering (BE), Electronics and Telecommunications Engineering

  2007 — 2011

• Manipal Institute of Technology

  Master of Technology (MTech), Digital Electronics and Advanced Communication

  2012 — 2014

Skills

• Microcontrollers
• Verilog
• Cadence Encounter
• Embedded C
• Physical Verification
• Matlab
• Pnr
• Arm Cortex-M
• Physical Design and Verification
• C
• Electronics Design Automation
• Tcl
• Python
• Kernel Programming
• Wireless
• Debugging
• Fpga
• Analog Circuit Design
• Device Drivers
• Soc
• Very-Large-Scale Integration (Vlsi)
• Digital Signal Processing
• Linux
• Perl
• Embedded Systems
• Static Timing Analysis
• Digital Electronics
• Vlsi
• Synopsys Primetime