Ganesh Bharadwaj

About Ganesh Bharadwaj

Current work: Managing SoC Projects at Intel.Work at QCOMM: Working on multiple process nodes (including 7nm, 10nm, 14nm, 28nm) for doing physical verification, DRC fixing, performing checks on DFYD, PERC, ERC, Softcheck, LVS cleanup and getting the chip/macro ready for base and metal tapeout. Work at Global Foundries: Product diagnostic and circuit analysis engineer at Global Foundries, where my work involves in providing circuit analysis for better understanding of failures in the circuits of our clients and provide methods for yield improvement. For my job, I perform DRC, LVS, ERC, parasitic extraction (PEX), layout to schematic conversion, run simulations in cadence Virtuoso/ADE, do mentor calibre DRC/DRV scripting, analysis of test data, analysis of nanoprobe data. I also do perl scripting to automate foundry related tasks. I also am involved in test circuit development and managing the Synopsis camelot database for the Technology Development team at Global Foundries. I have worked in projects for lot of clients like Qualcomm, Broadcom, M Star, Mediatek e.t.c and have a good understanding of CMOS circuits and process flow.

Experience

1. Senior Engineer

   Qualcomm

   Feb 2017 — Present · Chennai, IN

   In charge of Physical Verification in Qualcomm.

Education

• Nanyang Technological University Singapore

  Master of Engineering, IC design

  2010 — 2012

Skills

• Matlab
• Vlsi
• Verilog
• Semiconductors
• Linux
• Cadence Virtuoso
• Fpga
• C++
• Testing
• Simulations
• Cmos
• Soc
• Yield
• Ic
• Perl
• Semiconductor Failure Analysis
• Digital Ic Design
• Perl Automation
• Algorithms
• Programming
• Chip Testing
• Very-Large-Scale Integration (Vlsi)