Gagan Kumar
Lead Design Engineer (Signal and Power Integrity) at Cadence
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Gagan Kumar
3+ years of experience in SI/PI.Working in SI/PI domain for the Silicon Solutions Group(SSG) responsible for the design of DDR/LPDDR/GDDR IP in Cadence. Contributed on the PI side and responsible for PDN design for Microchip’s FPGA range. S parameter extractions using PowerSI, running full system PDN simulations (Impedance and Time Domain Simulations) consisting of VRM+Board+Package+Die on Keysight ADS, Synopsys Hspice. DC Drop Analysis using PowerSI and Siemens Hyperlynx.Ran DDR simulations on Siemen’s Hyperlynx. Have knowledge about termination techniques, I/O standards. Understand the flow of tools like Ansys HFSS for the SI simulation for checking discontinuity and optimising the structure at PCB level.Familiar with Cadence Sigrity Suite, Anysys HFSS, Ansys SI wave.
Experience
Lead Design Engineer
Jan 2026 — Present · Bengaluru, IN
Education
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
Bachelor of Technology - BTech, Electrical and Electronics Engineering
National Institute of Technology Karnataka
Master of Technology - MTech, VLSI Design
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