Gabriel Ve Vance
Senior Analog Design Engineer at Micron | Ex-TI | IIT Madras ’22
- Role
- Senior Analog Design Engineer at Micron Technology
- Location
- Kochi, KL, IN
- LinkedIn followers
- 500 followers
Experience
Senior Analog Design Engineer
Nov 2024 — Present · Bengaluru, IN
Design of Low Dropout Regulators for various specs• Design of a programmable PVT-accurate delay cell which is resilient against device mismatches. Delay modes can be switched on the fly with immediate response (patent pending)• Design of the control circuitry for a high speed multi rank memory system (patent pending)• Designed a novel multi step comparison based current limit mechanism for optimal power consumption for high voltage LDO.• Design of a novel ESD protection circuitry for high voltage LDO for 1ns supply ramps upto 20V, when external load cap isn\'t connected.• Design of a novel (custom) digitally assisted mechanism for undershoot clamping in LDO; using self-timed StrongArm latches as comparators.• Worked on Buck converter Compensator.• Design of Loopback to test receivers at 16Gbps data rate, compliant with LPDDR6 JEDEC; circuits : 2:1 serialiser and deserialiser, ultra fine programmable delay,
Education
Indian Institute of Technology, Madras
Bachelor of Technology - BTech, Electrical and Electronics Engineering
Indian Institute of Technology, Madras
Master of Technology - MTech, Electrical and Electronics Engineering
Gregorian Public School - India
High School
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