Gabbar Jadav
FPGA design | FPGA Prototyping & Emulation | RTL coding | ASIC design | Validation
- Role
- Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Gabbar Jadav
M.Tech graduate from NIT surathkal, Karnataka with 4+ years of experience in FPGA design, verification & validation Skills : HDL languages : Verilog, System verilog and basics of VHDLscripting : python,tclSimulation tools: Mentor Graphics Modelsim and Questa Sim, Xilinx vivado simulatorFPGA : Intel Cyclone IV, Cyclone V, Arria 10, Zynq Virtex-7.Tools used: Xilinx vivado,Intel Quartus II, IP megawizard, Protocmpiler, VCSEmulation & Prototyping: Palladium z1, HAP70,HAPS80Bug Report: jira
Experience
Staff Engineer
Apr 2024 — Present · Bangalore Urban, IN
Education
National Institute of Technology Puducherry
Bachelor of Engineering (BE), elctronics and communications engineering
2011 — 2015
Narayana Junior college, Hyderabad
Higher school level, MPC
2009 — 2011
National Institute of Technology Karnataka
Master of Technology (M.Tech.), Communication Engineering
2015 — 2017
Skills
- Microsoft Word
- Sql
- Windows
- Field-Programmable Gate Arrays (Fpga)
- Matlab
- Microsoft Office
- C
- Programming
- C++
- Powerpoint
- Microsoft Excel
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