Chenjun L.
SoC Design Verification Engineer at Apple
- Role
- Soc Design Verification Engineer at Apple
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Chenjun L.
Current System on Chip Design Verification Engineer at Apple Inc, specializing in block…
Experience
Soc Design Verification Engineer
Aug 2019 — Present · Austin, TX, US
Implement tests with SystemVerilog to comprehensively verify hardware attributes of future Apple devices, and as a result, 3 to 5 hardware attributes are put through validation weekly2. Strive through a 6-month-long project in Power Management used in future Apple electronics with a teammate, helping discover 7 hardware design bugs and improve the readability of the hardware specification by 60%3. Assist in the verification of a key component used in the communication device between R1 and M2 chips of Apple Vision Pro4. Participate in the verification documentation review of the “Always-on Display” feature used in iPhone 14 Pro and Pro Max5. Optimize verification of a debugging feature of future iPhones and iPads, boosting device functional coverage by 2%6. Invent a verification kit (vkit) for Global Trigger Interface (GTI) that increases the code reusability by 100% and can save up to 10 hours for other individual engineers (potentially help the company save $500+ from labor cost per GTI vkit usage)
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