Francina Paron
MTS Silicon Design Engineer
- Role
- Mts Silicon Design Engineer - Ip Verification Lead at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Francina Paron
Proficient Design Verification Engineer with 5+ years of industry experience. Specialized in UVM basedverification ensuring the functionality and reliability of complex hardware designs. Hands-on expertisein test planning, execution and debugging. Adept at delivering high-quality, validated products andposses good exposure to Ethernet protocol.
Experience
Mts Silicon Design Engineer - Ip Verification Lead
May 2024 — Present · Hyderabad, IN
Education
National Institute of Technology Warangal
Bachelor of Technology, ECE
2014 — 2018
Sri Chaitanya College of Education
Intermediate(12th), M.P.C
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
2020 — 2022
St. George's Grammar School's
10th Standard, ICSE
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