Jiauhua Frances Yeh

Analog Engineer at Intel Corporation

Role
Analog Engineer at 英特尔
Location
San Diego, CA, US
LinkedIn followers
500 followers

About Jiauhua Frances Yeh

Extensive experience in Professional Analog Integrated Circuit and Layout Designs. Mixed Signal Circuit design of High Power and High Performance Analog devices for Audio Products of Automobile and Home consumer markets. Very familiar with Integrated Class-D audio Amplifiers and Audio DSP (Digital Signal Processing). Color LCD Monitor with RGB Devices. RF Analog Power Management Products. Succeeded in outstanding design new products development, modification and system evaluation for Integrated Circuitry, components or parts of Electronic Equipment and Hardware system.Technical Skills : • Cadence Open Access, Design Synchronicity, Cadence ICAD 20.1 64b, Virtuoso-XL, SkillCAD, Cadence Assura and Place & Route.• DRC (Design Rules Check) and LVS (Layout Versus Schematic), ERC (Electrical Rules Check), Antenna Rules Check, Soft Check, Grid Check, Compare, LPE (Layout Parasitic Extraction), XRC, DBT (Database Translation), Shell Script, Mentor Graphics Calibre, K2 Chameleon VER, DIVA.• ARC (Assembly Rules Check), EM check (Electromigration Check), Power Plots, CLEO (ESD Latch-up), IO pads Voltage Clamp, Laff diff, Copper Metallization Rules, PG (Patten Generation) tape out procedure.• EDGE (Engineering Distributor Graphics) & EIS (Engineering Information System) tool• UNIX, Linux, Microsoft Word, Power Point, Excel.

Experience

  1. Analog Engineer

    英特尔

    Nov 2019 — Present · Hillsboro, OR, US

    Developed new product WiFi 6G design chips in CCG WCS group of RF Analog mmWave design for Fillmore Peak (FmP) project Samsung 14nmFF Process Technology. And WiFi 5G design chips in NGS group of mmWave RFIC Analog design for Niagara Summit (NAS) project TSMC 16nmFF Process Technology, High Band mmWave Power Amplifier with Whipple Point (WhP) project TSMC 28nm Process Technology and next generation 6G design for Yale Point (YaP) 45nmRFSOI Global Foundary Process Technologies.• Managed floorplan on layout of Comparator, TX ADC, DPLL, mmWave TX PA LB HB FBR, Inductor, Mesh cells.

Education

  • Hwa Hsia University of Technology

    Electrical Engineering, BS

  • Texas A&M University

    Certificate, Semiconductor processing

  • SDCCD

    Certificate, Linux Essential & Linux Server Technologies

    2016 — 2016

Skills

  • Physical Design
  • Cadence Virtuoso
  • Lvs
  • Cadence
  • Eda
  • Ic
  • Linux
  • Modelsim
  • Place & Route
  • Semiconductors
  • Drc
  • Spectre
  • Rf
  • Semiconductor Industry
  • Device Drivers
  • Debugging
  • Silicon
  • Analog Circuit Design
  • Microsoft Excel
  • Mixed Signal
  • Circuit Design
  • Integrated Circuit Design
  • Microprocessors
  • Tcl
  • Analog
  • Low-Power Design
  • Unix
  • Serdes
  • Shell Scripting
  • Pcb Design
  • Floorplanning
  • Bicmos
  • Power Management
  • Power Supplies
  • Verilog
  • Physical Verification
  • Microelectronics
  • Simulations
  • Microsoft Word
  • Electronics

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Jiauhua Frances Yeh — Analog Engineer at 英特尔 in San Diego, CA, US | Unifers