Fouzia Syed

About Fouzia Syed

Senior Validation Engineer with 4 years of experience in post-silicon validation of CPU, DDR4/DDR5 and GPU subsystems on x86 platforms. Specialized in Windows-based debug environments, JEDEC compliance testing, and HW/SW integration. Proficient in system-level diagnostics using WinDbg, WPR, and lab instrumentation tools. Supported hardware farm operations including setup, debug, and coordination with BIOS, firmware, and driver teams to ensure test coverage. Experienced in executing test plans, and basic use of Linux and scripting tools to support validation workflows.Technical Skills:1. Silicon Validation: CPU bring up, Post-Silicon Validation, JEDEC Compliance, Functional/Power/thermal/Stress/Regression Testing2. Debugging Tools: WinDbg, WPR, PerfMon, Crash Dump Analysis3. Instrumentation: Oscilloscopes, Logic Analyzers4. Programming: C, Python5. Automation & Infrastructure: Hardware Farm support, Sanity Scripts, Infrastructure Monitoring, Automation Frameworks6. Protocols: I2C, SPI, USB 3.0/3.1, MIPI7. System Tools: BIOS/VBIOS Updates, Firmware Flashing, Driver Testing (WDDM)Work Experience: 1. Supported day-to-day operations of the post-silicon validation farm, including system setup, debug, and coordination with BIOS/FW teams for continuous validation coverage.2. Performed CPU post-silicon bring-up and validation across Intel-based SoC platforms,validating reset flows, power sequences, and boot paths.3. Conducted functional and electrical validation of DDR4/DDR5 memory and GPU interfaces on Intel SoC platforms.4. Executed power, thermal, and stress testing of memory subsystems in alignment with JEDEC specifications and validation KPIs.5. Performed system-level debugging using WinDbg, WPR, and logic instrumentation to isolate performance and integration issues.6. Created and executed sanity test scripts to validate hardware and software readiness during regression and bring-up phases.7. Contributed to infrastructure improvements by reporting and resolving issues in hardware farm workflows and monitoring tools.8. Authored validation test plans, logs, and compliance reports for performance and reliability cycles.9. Participated in early silicon bring-up, including memory mapping checks, BIOS/VBIOS configuration tuning, and firmware flashing.10. Mentored junior validation engineers in JEDEC compliance testing, debug tools, and lab infrastructure protocols.

Experience

1. Senior Validation Engineer

   Wipro

   Apr 2024 — Present · Bengaluru, IN

   Results-driven engineer with over 4 years of experience in post-silicon validation, silicon bring-up, and system-level debugging. Strong expertise in SoC system qualification, high-speed IO protocols, power and performance validation, and automation using Python. Adept at collaborating with cross-functional teams to drive silicon debug and improve validation methodologies.

Education

• KL University

  Bachelor of Technology - BTech

  2017 — 2021