Feroz Khan Mohammad
DDR Verification Engineer at Cadence
- Role
- Ddr Verification Engineer at Cadence
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Feroz Khan Mohammad
Man needs his difficulties because they are necessary to enjoy success\"-Dr A.P.J Abdul Kalam• Computer Engineer with expertise in Hardware Design Verification. • Experience in Digital Design, ASIC Design Verification, Hardware Design and Verification. • Experience with Design and Development of low level firmware, algorithms targeting hardware platforms.• Hands on using Simulators like QuestaSim, Cadence tools• Familiar with Systemverilog Assertions (SVA), Functional and Code Coverage concepts.• Familiar with Test bench development, Execution and debugging, Developing RTL design.• Developed Monitor, BFM, Scoreboard and Generator, interfaces for different protocols and verified the functionality using Systemverilog. • Good Knowledge on logic implementation, UVM methodology.• Experience in generating scripts and responsible for automation of the process development. • Good knowledge on AMBA (APB, AXI).
Experience
Ddr Verification Engineer
Dec 2022 — Present
Education
The University of New Mexico
Master’s Degree, Computer Engineering
2015 — 2017
Kakatiya University
Bachelor of Technology (B.Tech.), Electronics and Communication Engineering
2009 — 2013
Skills
- Systemverilog
- Vhdl
- Network Security
- Application-Specific Integrated Circuits (Asic)
- Linux
- Modelsim
- C
- Programming
- Verilog
- Java
- Unix
- C++
- Python
- Algorithms
- Perl
- Embedded Systems
- Eda
- Testing
- Fpga
- Asic
- Asic Verification
- Very-Large-Scale Integration (Vlsi)
- Embedded C
- Xilinx Ise
- Pcb Design
- Field-Programmable Gate Arrays (Fpga)
- Rtl Design
- Tanner Eda
- Html
- Shell Scripting
- Microsoft Office
- Vlsi
- Tcl
- Computer Architecture
- Microprocessors
- Digital Electronics
- Matlab
- Microsoft Excel
- Cadence Virtuoso
- Microcontrollers
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