Fenil Dholakia

About Fenil Dholakia

12 years of experience in FPGA(Field Programmable Gate Array), IP (IntellectualProprietary) and Hardware Verification Development of C/C++ reference model and using DPIs to create an interface between System Verilog and C++ Developing Hardware Verification Language(HVL) based Re-usable and Automated constraintdriven verification environment with System Verilog and methodologies like UVM (UniversalVerification Methodology) and CDV (Constraint Driven Verification) Defining and developing Testbench Architecture, defining Verification strategy and closure goals Defining Testplan and creating Testcases Running tests, debugging failures and filing bugs on Verilog based RTL Defining and implementing Coverage and Assertions Hands on experience on PERL scripting, shell scripting, Makefiles Knowledge of AXI4,LPDDR4,SPI, Ethernet and ARINC818 (avionics) protocol Experience in hardware emulation, RTL synthesis and creating bitfiles Development and debugging the emulation C/SV testbench Executing DV and reliability testing at system levels and performing Six Sigma analysis of the Hardware instruments Good VBA scripting experience

Experience

1. Engineering Manager

   Intel

   Dec 2024 — Present · Bengaluru, IN

Education

• LDRP Institute of Technology and Research

  Bachelor of Engineering (BE), Electonics & Communication

  2007 — 2011

Skills

• Ncsim
• Microsoft Office
• Vlsi
• Functional Verification
• Field-Programmable Gate Arrays (Fpga)
• Very-Large-Scale Integration (Vlsi)
• Universal Verification Methodology (Uvm)
• Open Verification Methodology
• Application-Specific Integrated Circuits (Asic)
• Soc
• C
• Fpga
• Asic
• C++
• Linux
• Modelsim
• Systemverilog
• Verilog
• Amba Ahb
• Uvm
• Perl
• Debugging
• I2c
• System on a Chip (Soc)