Feminavathi Arumugam

About Feminavathi Arumugam

Working as a RTL Design and Verification Engineer at HCL Technologies and also have a good knowledge in verilog and system verilog. I am a highly motivated and enthusiastic individual, who enjoys the challenge of working within demanding environments. My professional interests are verilog and SystemVerilog, Verification methodology,VLSI Verification Flow. Looking forward to apply my knowledge and skills into projects and work along with other enthusiastic team members to solve real world challenging problems. Always ready to learn new technologies to grow and improve on existing skills.

Experience

1. Senior Software Engineer(Rtl Design and Verification)

   HCLTech

   Nov 2018 — Present · Chennai, IN

Education

• Anna University Chennai

  B.E, ECE

  2012 — 2016

• College of Engineering, Guindy

  M.E, VLSI Design

  2016 — 2018