Fakeerappa Madiwalar
Senior Memory Layout Engineer
- Role
- Memory Layout Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Fakeerappa Madiwalar
Skilled in Design Rule Checking (DRC), Microsoft Office, Layout Versus Schematic (LVS), Cadence Virtuoso, and C (Programming Language). Strong engineering professional with a DIPLOMA focused in Electronics and Communication Engg from KLE\'S POLYTECHNIC,BAILHONGAL.
Experience
Memory Layout Engineer
Feb 2022 — Present · Bengaluru, IN
Education
Visvesvaraya Technological University
Bachelor of Engineering - BE
KLE'S POLYTECHNIC,BAILHONGAL
DIPLOMA
2015 — 2018
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