Fahad M

About Fahad M

Highly skilled and motivated VLSI engineer with years of experience in the…

Experience

1. Design Verification Engineer

   Wipro

   Aug 2021 — Present · Bengaluru, IN

   Highly skilled and motivated VLSI engineer with 2.2 years of experience in the field.Possess a strong foundation in digital design concepts and proficient in System Verilog,Verification Methodologies and Industry-standard EDA tools such as Synopsys VCS andCadence. My expertise lies in the verification of complex IP & SoC designs using UVMmethodologies, and have experience in developing testcases, and debugging complexdesigns.Project 1: Parser IP VerificationDescription : Parser IP is a part of Network Interface card placed in servers andaccepting data packets from different networks and extraction the packetfields.Roles & Skills-Worked on Developing testcases using VIP with Understanding of protocols-Data Link Layer (Ethernet), Network layer (IP4, IP6, vlan), Transport Layer-(UDP, TCP) & Encapsulation protocols (Vxlan, Geneve, GRE, Rocev2)-Worked on Scoreboard development & Checksum verification-Developed Functional Coverage and Code coverage model to track theprogress of the verification-Worked on running Local & Farm RegressionsProject 2: IOFS SoC VerificationDescription : IOFS Soc is a Network Interface Module consist of severalIP\'s like (BNIC/OVS) which is placed in servers, It has the functionality tosend and receive packets. The purpose of the module is to increase theefficiency by reducing the load in serversRoles & Responsibilities-Worked on accessing an verifying CSR Registers for BNIC / OVS IP\'s-Worked on data path packet transmission testcases and debugging it-Developed Testcases for all CSR\'s & debugging them-Currently working on running regressions and developing testcases for datapath entries and end to end check

Education

• Campion Anglo Indian Higher Secondary School

  High School

  2002 — 2017

• Saranathan College of Engineering

  Bachelor of Engineering - BE

  2017 — 2021