Eric S.
Verification Team Lead & Architect - Vision and Adas @NXP Semiconductors
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WORK HISTORY
Verification Team Lead & Architect - Vision and Adas @NXP Semiconductors
Kanata, CA
Responsibilities:* Manage Risk, Schedule, Tasks, Hiring, Lead & Mentor team and Intern * Develop schedules and provide project tracking matrix * Working with architects & customers to develop specifications * Establish Hardware/Software requirement for verification * Evaluate and Select tools for the verification platform * Architect and Implement Verification Platform in System Verilog (UVM), C/C++, SystemC, … * Architect and implement portable test methodology to support Verification, FPGA Validation, SoC * Verification and bring-up * Write test stimulus for functional & code coverage * Write design specifications & DV test plan.* Code UVM assertion-based test-benches to verify the design * Debug complex system-level simulations * Model the design in C/C++, SystemC, … * Emulate the design on FPGA-based systems * Resolve & Validate silicon bring-up design issues
ABOUT ERIC S.
Solid experience gained in leading, architecting, design, implementation and debugging of ASICs, FPGA’s, SoC and Software in ADAS, Space System, wireless audio device and data communications. Knowledge of Verilog and VHDL, strong knowledge of design and verification tools (System Verilog, UVM, System C, C/C++). Knows how to properly validate and push devices/software to their limit in term of resource usage. Skills to solve the toughest ASIC, FPGA and Software; Architecture, design and verification problems. Specialties: Asic Verification Embedded Software design & Verification Languages: System Verilog, OVM, UVM, C/C++, Python, Verilog, VHDL, TCL, PERL, ASM, SystemC, Vera, bash/tcsh scripting.
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