Eric Foreman

About Eric Foreman

Hi there! At IBM I am responsible for the development of the timing methodology…

Experience

1. Senior Timing Sta Ssta Development Engineer

   IBM

   Feb 2001 — Present

   I am the team lead for timing and noise methodology development in IBM Systems for all server power systems, z mainframe processors, and SOC/ASIC designs. My work is within chip design organization, and I work side by side designers to achieve our chip tape-outs.I have supported the tape-out of many designs in numerous technology nodes both in IBM OEM ASICs and IBM Server. I have expertise in timing, chip design, software development, and manufacturing process variation. I developed an industry first variation-aware statistical static timing sign-off methodology to account for process variations, voltage binning, dynamic voltage frequency scaling, and noise due to cross-talk. My latest work involves adding Machine Learning and AI into chip design, and building automation tools for clock and constraint command generation. The constraint system works across hierarchy and fully compatible with SDC.