Eric Cw Chan

WORK HISTORY

EDUCATION

SKILLS

ABOUT ERIC CW CHAN

Technical skills and experience: o DFT related - Performed and debugged gate and RTL simulation for developing functional test patterns (3D engine, display controller, memory IO)- Generated and optimized at-speed memory BIST patterns - Scan insertion, EDT, coverage optimization - Generated stuck-at fault and transition-delay fault patterns using Mentor Graphics ATPG tool - Conducted scan diagnostics using Mentor Graphics Yield Assist - Familiar with structural test features, such as, JTAG, boundary scan, Scan, memory BIST, IO BIST, functional BIST o Test engineering related - Developed, consolidated and documented the overall product test plan and test flow - Debugged and implemented both structural and functional ATE test coverage on digital IP (graphics core, display controller, etc.) and analog IP (DAC, PCIE, TMDS, Display Port, etc.) blocks - Developed speed grading and power profiling methodology - Full ASIC characterization including timing margin, DC IO parametric, speed and power profiling, voltage marginality, temperature sensitivity, manufacturing process sensitivity - Root-caused manufacturing defects, tackled infant mortality and lowered DPM Soft skills and experience: o Leadership and program management - Test team lead for multiple GPU projects - Led a team of ten engineers in new silicon bring-up, developed product development plan, coordinated team efforts and responsibilities, scheduled resources, negotiated milestones and communicated with cross functional teams, presented overall progress to upper management - Hosted series of meetings for team sync up, drumbeat o Team player - Worked with various DFT and design teams from different geographical offices - Transferred knowledge to remote product teams through conferences and on-site trainings, assisted them in product deployment at Offshore Subcontract Assembly and Test Manufacturers (OSAT)