Eric A Foreman
- Role
- Senior Development Engineer Scientist, Team Lead, and Ibm Master Inventor at IBM
- Location
- Fairfax, VT, US
- LinkedIn followers
- 500 followers
Experience
Senior Development Engineer Scientist, Team Lead, and Ibm Master Inventor
Feb 2001 — Present
I am the team lead for timing and noise methodology development in IBM Systems for all server power systems and z mainframe processors. I have supported the tape-out of hundreds of designs in numerous technology nodes both in IBM OEM ASICs and IBM Server. I have expertise in timing, chip design, software development, and manufacturing process variation. I developed an industry first statistical static timing sign-off methodology to account for process variations, voltage binning, dynamic voltage frequency scaling, and noise due to cross-talk. My latest work involves adding Machine Learning and AI into chip design, and building automation tools for clock and constraint command generation.
Education
Penn State University
BS, Electrical Engineering
1994 — 1999
Penn State University
Minor, Mathematics
1994 — 1999
Boston University
MS, Electrical Engineering
1999 — 2001
Clarkson University
PhD, Electrical and Computer Engineering
2006 — 2011
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