Emmanuel Muthu

About Emmanuel Muthu

RTL: Verilog Synthesis Tools: Xilinx ISE 12.4,Quartus II,Design Compiler Devices: Virtex 5,Virtex 4,Spartan 3,Spartan 6 and Stratix IV Simulation Tool: ModelSim,VCS DSP Tool: System Generator STA Tools: Xilinx P&R, PrimeTime Debugging Tool: Chiipscope Bus Protocol Standards: I2C, SPI and SFPDP Domain Knowledge: Design & development of efficient RTL with Timing closureSpecialties: Involved in requirement study and analysis, preparation and review of Documents including Register Details, RTL & Schematic design and simulation for functional & timing closure. Responsible for coordinating with Hardware Design Team and Software Design Team. Client Interaction for ensuring requirements, accountable for proto Testing & qualification. Prepared & reviewed test cases, generated test report and test log.

Experience

1. Senior Asic Engineer

   NVIDIA

   Apr 2013 — Present

Education

• M S Ramaiah School of Advanced Studies ,Bangalore

  PG Diploma

  2006 — 2006

• Bannari Amman Inst of Tech

  BE

  2002 — 2006

Skills

• Vlsi
• Verilog
• Fpga
• Rtl Design
• Timing Closure
• Digital Signal Processors
• Static Timing Analysis
• I2c
• Modelsim
• Xilinx Ise
• Hardware Architecture
• Validation
• Xilinx
• Spi