Emilio Yero
Technologist
- Role
- Principal Engineer at Silvaco Inc
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Principal Engineer
Feb 2022 — Present · Santa Clara, CA, US
Skills
- Low-Power Design
- Sram
- Cadence Virtuoso
- Debugging
- Silicon
- Very-Large-Scale Integration (Vlsi)
- Analog Circuit Design
- Eda
- Field-Programmable Gate Arrays (Fpga)
- Power Management
- Mixed Signal
- Circuit Design
- Fpga
- Asic
- Cmos
- Integrated Circuits (Ic)
- Semiconductor Industry
- Drc
- Rtl Design
- Ic
- Analog
- Primetime
- Systemverilog
- Timing Closure
- Static Timing Analysis
- Integrated Circuit Design
- Dft
- Hardware Architecture
- Application-Specific Integrated Circuits (Asic)
- Verilog
- Flash Memory
- Physical Design
- System on a Chip (Soc)
- Soc
- Semiconductors
- Vlsi
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