Emil Sunny

About Emil Sunny

Experienced in IP/FPGA Development - architecture, design, RTL coding, simulation, Synthesis, implementation, timing closure and documentation.• Have worked on protocols like PMA, 10G Base-R MAC+ PCS/PMA, MRPHY (10M to 10G) base-X, Low latency 40G.• Have good knowledge and experience in System Verilog, Verilog, TCL scripting, Shell scripting, VHDL.• Have worked with EDA tools like Spyglass, Questasim, VCS-MX, ModelSim, Cadence NCSim.• Have good experience in FPGA design tools like Xilinx Vivado,Intel Quartus• Experienced in XilinxFPGA bring up. Have used Vivado’s ILA and IBERT in various stages of debugging and testing.• Experience in data centre related projects.• Have worked on partial reconfiguration with Xilinx Fpga.• Experience on lint analysis, CDC/analysis and closure.• Experience in using project support tools including Perforce, GIT.

Experience

1. Ip Logic Design Engineer

   Intel

   Jun 2022 — Present · IN

   Transciever PHY.Ethernet.RTL design.Micro architecture.Clock Scheme.Reset Scheme.CDC/LINT

Education

• Cochin University of Science and Technology

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2011 — 2015

• Model Engineering College

  Master of Technology - MTech, Vlsi & embedded system

  2017 — 2019