Elisa C.
ASIC verification engineer
- Role
- Asic Verification Engineer at Eridu
- Location
- Fremont, CA, US
- LinkedIn followers
- 500 followers
About Elisa C.
Extensive experience in the ASIC verification field, using SystemVerilog and UVM to create new testbenches from scratch and defining and implementing test plans. Goal oriented and dynamic professional with proven ability to deliver bug free silicon. Recognized among peers as having an excellent work ethic and striving to achieve both individual and team goals on time.
Experience
Asic Verification Engineer
Jul 2025 — Present · Saratoga, CA, US
Education
Georgia Institute of Technology
Some coursework from Georgia Tech OMSCS (incomplete), Computer Science, Computing Systems specialization
Universitat Autònoma de Barcelona
MS, Computer Engineering
Universitat Autònoma de Barcelona
BS, Computer Engineering
IES La Llitera (Tamarite, Huesca, Spain)
High School Diploma
Skills
- Pcie
- Verilog
- Fpga
- Asic
- System on a Chip (Soc)
- Functional Verification
- Oop
- Debugging
- Logic Synthesis
- Tcp/Ip
- Soc
- Field-Programmable Gate Arrays (Fpga)
- C
- Aop
- Static Timing Analysis
- Tcl
- Linux
- Logic Design
- Application-Specific Integrated Circuits (Asic)
- Embedded Systems
- Eda
- Rtl Coding
- Systemverilog
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