Eldhose Joy
ASIC Physical Design Engineer | Physical Design, Static Timing Analysis
- Role
- Senior Physical Design Engineer at HCLTech
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Eldhose Joy
Physical Design EngineerHands on experience in - Synopsys Fusion Compiler - Synopsys IC Compiler 2 - Prime Time - Redhawk - StarRC - Layout Editor - Linux OS - TCl Scripting - Caliber (DRC & LVS)Skills in - Physical Design (Floorplanning, Placement, Clock Tree Synthesis, Routing, All signoff)- Static Timing Analysis - EM-IR - Full custom layout - Drawing
Experience
Senior Physical Design Engineer
Jul 2025 — Present
Education
APJ Abdul Kalam Technological University
Bachelor of Technology - BTech
2015 — 2019
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