E. J. Tsangaris

Experience

1. Analog Mixed-signal Ip - Tools & Infrastructure

   Synopsys Inc

   Mar 2026 — Present · Chandler, AZ, US

Education

• Carnegie Mellon University

  MS, Electrical Engineering

  1996 — 1997

• Carnegie Mellon University

  BS, Electrical & Computer Engineering

  1992 — 1996

Skills

• Logic Design
• Timing Closure
• Project Planning
• Systemverilog
• Low-Power Design
• Very-Large-Scale Integration (Vlsi)
• Dft
• Asic
• Project Management
• Debugging
• Semiconductors
• Mixed Signal
• Vlsi
• Static Timing Analysis
• Application-Specific Integrated Circuits (Asic)
• Verilog
• Rtl Design
• Ic
• Pcie
• System on a Chip (Soc)
• Cmos
• Integrated Circuits (Ic)
• Ddr
• Theory of Constraints
• Analog Circuit Design
• Soc
• Xscale
• Formal Verification
• Primetime