Eirik Esp
IP Design Manager, caching and coherency fabrics at Intel Corporation
- Role
- Server Ip Development Manager at Intel
- Location
- Nashua, NH, US
- LinkedIn followers
- 500 followers
About Eirik Esp
Specialties: System integration, SOC ASICs.
Experience
Server Ip Development Manager
Apr 2017 — Present · Hudson, MA, US
Developing complex caching and homing agent supporting both single and multi-socket cache coherency used in all Intel server products for multiple generations. Also delivered on high speed programmable mesh fabric and bridging for Intel server products, Managing a team of ~20 engineers, delivering generation on generation enhancements and performance targets for multiple products and derivatives on Intels Server Roadmap. I manage day to day execution for RTL development, pre-si verification, and basic timing convergence, setting priorities balancing near term vs long term goals, coordinating development activities with partners and internal customers, and building a team with the right skills and capabilities to meet current and future development goals. Also working closely with emulation and formal verification teams to deliver high quality IP ready for tapein.
Education
University of Wyoming
Master's degree, Electrical and Electronics Engineering
1985 — 1992
Skills
- Fpga
- Asic
- Hardware Architecture
- Integration
- C
- Vlsi
- Semiconductors
- Network Processors
- C++
- Debugging
- System Architecture
- Soc
- Ic
- Rtl Design
- Field-Programmable Gate Arrays (Fpga)
- Systemverilog
- Emulation
- Vhdl
- Simulations
- Intel
- Computer Architecture
- Verilog
- Microprocessors
- Perl
- Embedded Systems
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