Edward Leo

Experience

1. Contract Sr Fpga Engineer Designing Fpgas for Arinc Based Aircraft Interface Devices (Aid)

   Collins Aerospace

   Jun 2022 — Present · Cedar Rapids, IA, US

   Added features to the FPGA that facilitated and controlled the entire AID network.* Handled all aspects of FPGA design from conceptualization, documentation (incl. DO-254) and HDL to synthesis and lab debug.* FPGA debug was done on a Linux controlled AC-701 development board, as well as a later on the custom AID unit board.* Followed design procedures and wrote documents conforming to DO-254 (DAL-D) standards.* Techniques: AXI, PCI-E, RTL Algorithms & Data Paths, SPI, IIC, UART, CAN, ARINC 429 / 708 / 717; Multiple Clock Domains.* Tools: Linux, System Verilog, VHDL, Vivado w/ Chipscope, Artix 7, QuestaSim, SVN, JIRA, JAMA, PREP, Clocks to 125 MHz.

Education

• Rochester Institute of Technology, Rochester, NY

  BSEE, Electrical Engineering

  1984 — 1987

• University of California San Diego Ext., San Diego, CA

  Certificate In DSP Engineering, DSP Engineering

  2011 — 2011

• University of California San Diego Ext., San Diego, CA

  Advanced System Verilog

  2012 — 2012

• University of California Santa Cruz Ext., San Jose, CA

  Advanced Modeling Techniques With VHDL

  1995 — 1995

• University of California Santa Cruz Ext., San Jose, CA

  Digital Design Using VHDL

  1995 — 1995

• Mohawk Valley Community College, Utica, NY

  Programming In C

  1989 — 1989

• University of California Santa Cruz Ext., San Jose, CA

  Logic Synthesis (using Synopsis Design Compiler)

  1995 — 1995

• Mohawk Valley Community College, Utica, NY

  AASEET, Electronics Technology

  1981 — 1983