Edvard Mkrtchyan

Principal Member of Technical Staff @Analog Port

Plano, TX, US
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Oct 2022 — Present

Principal Member of Technical Staff @Analog Port

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McKinney, TX, US

EDUCATION

2004 — 2006

Yerevan State University

Master of Science, Physics of Semiconductors and Microelectronics

1999 — 2003

Yerevan State University

Bachelor of Applied Science (BASc), Radiophysics and Electronics

SKILLS

Cmos Analog/Mixed Signal DesignAsicStatic Timing AnalysisAnalogEmbedded SystemsEdaAlgorithmsPhysical DesignFunctional VerificationDebuggingCmosIntegrated Circuits (Ic)Very-Large-Scale Integration (Vlsi)Application-Specific Integrated Circuits (Asic)SimulationsSystem on a Chip (Soc)R&DRtl DesignIcIntegrated Circuit DesignAnalog Circuit DesignVerilogResearch and Development (R&D)Mixed SignalCircuit DesignSemiconductorsTestingVlsiSocTiming ClosureSystemverilogSpice

ABOUT EDVARD MKRTCHYAN

PROFESSIONAL SUMMARYPrincipal AMS Design Engineer with over 20 years of industrial experience in CMOS IC Design. Participated in over 40+ projects with high volume productions. Experienced in complete product development lifecycle: from initial conception through design, verification, fabrication & testing. Extensive experience of working with different teams and customers across the world (USA, CA, Europe, Egypt, Armenia, Macau, India). Driven by project and team success.TECHNICAL SKILLS • Principal Analog/Mixed-Signal engineer with primary focus on the design of high-speed serial interfaces (LVDS, HSIC, USB 2.0, USB 3.0, USB 3.1,USB4/Redriver, PCIe, HDMI 1.4, MIPI D-PHY, fast GPIOs, Photonic SerDes, UCIE).• AFE level development (system modeling, creation of sub cells specifications, area estimation, top level layout floorplanning/supervision).• Transistor level design of analog/mixed building blocks (ADC, DAC, SERDES, High Speed TX/RX, FIR Filters/Equalizers, CTLE, DFE, Custom Coils/T-Coils, Crystal Oscillators, full on chip Precision Current/Voltage References, Multipliers/Squarers, Opamps, Comparators, Level-Shifters, Voltage Regulators, I/Os.). Significant experience in overstress protection techniques. Experience on ESD protection strategies and GPIO design. • Implementation of Auto Adaptation Algorithms such as Sign-Error LMS, Gradient-Sign LMS and Sign-Sign LMS, AGC, Offset Correction Loops etc. • Experience in deep submicron planar CMOS (from 180nm down to 20nm) and FinFet (16nm, 6nm) analog design in most fabs and processes.• 2+ years of Analog Layout Design experience (planar CMOS technologies only).Block level and top level analog layout design.• Solid experience in system verification (Co-Simulation, Reliability/Ageing and EM/IR-Drop analysis).• Expertise in developing documentation/reports.• Strong team player with leadership qualities. Stress resistant with ability to work effectively under aggressive schedules. Highly motivated, quick learner with multi task skills. Outstanding communication, interpersonal and time management skills.EDA/ PRODUCTIVITY Tools• Cadence toolchain• Synopsys toolchain• Siemens toolchain

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