Edrin J Kamil

About Edrin J Kamil

Expertise in developing the object oriented-self checking verification environment using System Verilog and UVM Methodology from scratch. Expertise in Functional Verification using Verilog, System Verilog, C, OVM, UVM Methodologies.Protocol experience of AMBA AHB Lite, AXI, APB, Cache, Ethernet, I2C. OCP 2.0, SPI.Experience in IP and SoC verification.VIP development of OCP2.0, APB in SV-UVM.Experience in Assertion based verification, Coverage closure.Tools used are, Cadence Incisive, Model Sim, Synopsys VCS.

Experience

1. Staff Engineer

   Analog Devices

   Jul 2023 — Present · Bengaluru, IN

Education

• ANNA UNIVERSITY

  Bachelor Degree, Electronics and Communication Engineering

  2005 — 2009

• PG Diploma in VLSI (CDAC)

  PG Diploma, VLSI Design

Skills

• Rtl Design
• Functional Verification
• Perl
• Eda
• Universal Verification Methodology (Uvm)
• Soc
• C++
• Verilog
• Vhdl
• Cadence
• Uvm
• Amba Ahb
• Vlsi
• Rtl Coding
• Modelsim
• Ethernet
• Semiconductors
• Fpga
• Asic
• Tetramax
• System on a Chip (Soc)
• I2c
• Static Timing Analysis
• Synopsys Tools
• Integrated Circuit Design
• Systemverilog
• Open Verification Methodology
• Tcl