E. Venkata Ramesh

About E. Venkata Ramesh

Worked on a flat chip place and Route. Responsibilities were doing Project Setup, chip floor planning, macro placement, IO pad placement, Power planning, Placement, Clock tree Generation, Routing, Parasitic Extraction, Static Timing Analysis, DRC, LVS and Antenna checks. • Performed many ECO iterations to reach timing closure • Good Knowledge on physical design tools like IC Compiler, IC Validator, Cadence Virtuosos • Basic scripting knowledge of TCL, PERL • Good understanding of CMOS concepts and Circuit Theory fundamentals • Good knowledge of Digital Design Concepts • Good knowledge of IC Fabrication Process • Basic knowledge of power reduction techniques

Experience

1. Graphics Hardware Engineer

   Intel

   Sep 2015 — Present · Bengaluru, IN

Education

• JNTUK University

  B.Tech, Electronics and Communication Engineering, 70%

  2007 — 2011

• Nalanda Junior College

  12th, MATHS, PHYSICS, CHEMISTRY, 89%

  2005 — 2007

• Everest English School

  10th, MATHS, SOCIAL, PHYSICS, BIOLOGY, 88%

  1995 — 2005

• Vellore Institute of Technology

  Master’s Degree, VLSI DESIGN, 8.1/10 CGPA

  2012 — 2014