Savita Maurya Shah
Pre-Silicon Design Quality & Reliability Engineer @ Intel | Semiconductor Reliability | TDDB • BTI • HCI • EM | Wafer-Level Reliability | Device Fabrication | PhD in Semiconductor Reliability | International Speaker
- Role
- Pre-si Design Qnr Engineer at Intel
- Location
- Mumbai, MH, IN
- LinkedIn followers
- 500 followers
About Savita Maurya Shah
Semiconductor Reliability Engineer with 12+ years of experience spanning pre-silicon…
Experience
Pre-si Design Qnr Engineer
Sep 2021 — Present
Support CPU & Hard IP development on Intel (14A, 18A, Intel 3, Intel 4) and TSMC (N2, N3, N5, N7) nodes- Perform pre-silicon simulations, design audits, and reliability verification (PV/RV)- Mitigate circuit marginalities (BTI, HCI, TDDB, EOS, EM, package interactions)- Lead quality reviews, risk assessments, and cross-team collaboration across design and manufacturing- Provide technical guidance to junior engineers and drive program execution.
Education
Banasthali Vidyapith
M.Tech, VLSI, RF MEMS Switches, Satellites
2006 — 2008
Indian Institute Of Information Technology Allahabad
Doctoral, Microelectronics
2010 — 2015
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