Ching Hsueh
Semiconductor Engineer | Foundry Interface Engineer | Server/Data Center Product Development Engineer | Process, TCAD, DFM, Integration, Yield | Ex- AMD, TSMC | UPMC Paris | Ph.D. in Physics
- Role
- Dfm Smts Engineer at AMD
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Ching Hsueh
13+ Years of Semiconductor Expertise**- Extensive experience at TSMC, Samsung, and AMD, covering R&D to high-volume manufacturing (HVM) for 14nm to 2nm nodes- Skilled in process integration, yield enhancement, device development, design enablement, customer engineering, and program management- Delivered solutions for FinFET design, plasma etch simulation, and BEOL/MEOL yield optimization-**5+ Years of Leadership**- Led cross-functional teams under dynamic, time-sensitive conditions, achieving 100% milestones for 5nm/6nm AI product ramps at AMD- Collaborated with foundries and internal stakeholders to streamline NPI and enhance foundry operations- Recognized for strategic planning and execution in high-pressure environments-**Accomplished Engineer**- Published in *European Physical Journal* and *Chemical Engineering & Processing*- Earned 8+ awards, including AMD Spotlight Awards, Samsung Best Paper finalist, and TSMC Bright Idea Award, for yield, cost, and process innovations- Contributed to industry through technical expertise and mentorship-**Key Achievements**- At TSMC (2012–2018): Designed 5nm FinFETs with Synopsys TCAD, resolved 7nm CVD fin bending using COMSOL, and released 16nm Ti-Silicide CIP recipes, cutting costs by 40% and improving uniformity/throughput by 44%/66%- At Samsung (2018–2021): Enhanced 14nm BEOL yield and launched RMG CIP recipes for yield improvement- At AMD (2021–2025): Improved yield modeling by 25%, automated BEOL weak pattern detection, and led 5nm/6nm AI product ramps-**Specialties**- Foundry Engineering, Process Integration, Yield Enhancement, DFM, BEOL/MEOL Yield Analysis, TCAD Simulation, COMSOL, Plasma Etch Simulation, Data Analysis (JMP, Python, PowerBI), Program Management, SPC, Continuous Improvement, Vendor Management, Quality, Reliability, NPI.My Ph.D. in Physics from Université Pierre et Marie Curie and trainings at TSMC/ASML drive my innovation. I mentor engineers and explore AI-driven process optimization. Connect via email to discuss semiconductor advancements!Skills- Career Coaching- Yield Prediction- Design for Manufacturing (DFM)- Back-End-of-Line (BEOL) Yield Analysis- PowerBI Dashboards- TCAD Simulation- Project Management
Experience
Dfm Smts Engineer
Sep 2021 — Present
Education
National Central University
Bachelor's degree, Physics
2002 — 2006
National Central University
Master of Science (M.S.), Physics/Biophysics
2006 — 2008
Pierre and Marie Curie University
Doctor of Philosophy (Ph.D.), Physics
2009 — 2012
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