Ratnadeep Dutta

About Ratnadeep Dutta

With over 11+ years of experience in Design for Test (DFT) implementation. My expertise spans end-to-end DFT processes, including architecting test, DFT IP generation, RTL integration scan insertion, MBIST implementation, ATPG, pattern validation etc. ensuring high-quality deliverables. I work collaboratively with cross-functional teams to optimize the process and improve the quality of the test.I lead a Cores IP DFT team (CPU, GPU) and am responsible for the end to end DFT solutions. Previously, I led SoC ATPG, GLS, and Post Silicon efforts for Intel\'s visual technologies and discrete graphics products.

Experience

1. Senior Staff Engineer

   Samsung Semiconductor

   Feb 2023 — Present · Bengaluru, IN

   CoreIP Implementation:• End to End DFT implementation of ARM Hayes (A-520), Hunter (A-720), Hayden DSU, Ananke (A-55) cores.• DFT scan rules check using spyglass.• Scan insertion using Fusion Compiler and collaboration with cross functional teams for driving better QoR.• Test Point Insertion using Fusion Compiler and Spyglass to improve ATPG coverage.• Ownership of Core level ATPG and pattern validation.• MBIST implementation using LV flow and tessent flow.• Shared bus MBIST implementation of ARM cores.• MBIST verification in RTL simulation and GLS.SoC Development:• Cluster level and SoC level ATPG using Tetramax and validation using Cadence Xcelium.• ATE generation from wgl using TESTMAX Vtran. • Playback simulation of deliverable scan and mbist ATEs. • Analyzing and debugging the silicon failures.

Education

• M. S. RAMAIAH UNIVERSITY OF APPLIED SCIENCES

  Master of Technology - MTech, VLSI system design

  2016 — 2019

• University Institute of Technology, The University of Burdwan

  Bachelor of Engineering - BE, Electronics and Communication Engineering

  2010 — 2014

Skills

• Gate Level Simulation
• Very-Large-Scale Integration (Vlsi)
• C
• Power Aware Dft
• Automatic Test Pattern Generation (Atpg)
• Linux
• Memory Bist
• Soc
• Vlsi
• Boundary Scan
• Asic
• Java
• Verilog
• Scan Insertion
• Dft
• Confirmal Lec
• Matlab
• Embedded Systems
• Coverage Analysis
• C++