Drashti Patel

About Drashti Patel

7.5+ years of working experience with RTL design using Verilog/System Verilog (SV).• Proficient in Verilog / System Verilog/ VHDL RTL design languages.• Proficient in microarchitecture, digital design / IP design and RTL implementation from high-level design specifications.• Hands-on experience with energy-efficient and complex low-power logic designs (Island architecture).• Proficient in working with complex multi-clock and multi-reset domain architecture and multiple pipelining stages.• Hands-on experience working with sub-system level design and front-end chip design flow.• Good experience in working with multi-clock, multi-reset domain and complex power domain design.• Proficient in working with sub-system level IP having standard on-chip interfaces (AMBA protocols) like AHB / AXI / APB.• Fluent in debugging issues related to ASIC design front-end checks like - compilation, CDC, Lint, Synthesis, timing closure, STA, PTPX, power checks, etc.• Good understanding of scripting languages like Python, and shell.• Strong problem-solving skills and effective communication skills.• Efficient in handling the ownership of a sub-system level IP for multiple projects simultaneously.

Experience

1. Staff Engineer

   Qualcomm

   Dec 2023 — Present · Bengaluru, IN

Education

• Nirma Institute Of Technology

  Master’s Degree

  2013 — 2015

• GOVT Engineering College, Gandhinagar

  Bachelor of Engineering (B.E.)

  2009 — 2013

Skills

• Verilog
• Fpga
• Microsoft Office
• C
• Cdc
• Xilinx Ise
• Pcb Design
• Very-Large-Scale Integration (Vlsi)
• Microcontrollers
• Bluetooth
• Matlab
• Assembly Language
• Xilinx
• Rtl Coding
• Secure Shell (Ssh)
• Rtl Design
• Sta
• Digital Signal Processing
• Soc
• Vhdl
• Simulations
• Radar
• Algorithms
• Shell Scripting
• Perl
• Embedded Systems
• Research
• Integrated Circuit Design