Neha Gupta
Lead Design Engineer
- Role
- Lead Design Engineer at Cadence
- Location
- Pune District, MH, IN
- LinkedIn followers
- 500 followers
About Neha Gupta
Coding Languages: Verilog, VHDL, C, C++, Image processing+ Software/Tools: Xilinx Vivado, Xilinx ISE, Vitis HLS, Lattice, Cadence Virtuoso, Cadence-LayoutXL, Synopsys-HSPICE, Mentor Graphics- Calibre+ FPGA protocols: SPI, I2C, UART, AXI, MIPI-CSI2+ Hardware Platforms: Xilinx Artix 7, Virtex 7, ZYNQ ultrascale+ MPSoC, Kria K26 SOM boardand Basys3 board.+ Debugging tools: Vivado ILA and Chipscope+ Chip design: ASIC Full custom VLSI chip design
Experience
Lead Design Engineer
May 2024 — Present · Pune, IN
Education
Indian Institute of Technology, Indore
Doctor of Philosophy, Design Techniques for Radiation Hardened, Reliable and Low-Power Circuits
Institute of Engineering & Technology DAVV, Indore
Master of Engineering - MEng, Electrical, Electronics and Communications Engineering
Truba Group of Institutes, Bhopal
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
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