Manoj Pandey

Associate Professor (Ece) & Dy Controller of Examinations @Sarala Birla University - Sbu, Ranchi

Ranchi, JH, IN
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Oct 2025 — Present

Associate Professor (Ece) & Dy Controller of Examinations @Sarala Birla University - Sbu, Ranchi

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Ranchi, IN

EDUCATION

2009 — 2016

Sant Longowal Institute of Engineering and Technology

Ph.D, FPGA, Reconfigurable Computing Systems, Video/Image Processing

2005 — 2007

Tezpur University

M.Tech

ABOUT MANOJ PANDEY

Thanks for reaching out to my profile.# Presently, I hold the position of Associate Prof. & Head of the Department of Electronics & Communication Engineering (ECE).#For last 18 years, I am Involved at University Level Teaching & Research under the UG, PG & PhD courses of Electronics & Communication Engineering and Computer Science Engineering. During this period, I worked on various academic & admin positions like Director, IQAC, Head of the Department, Research Coordinator, Program/Course coordinator, Coordinator of Incubation Cell & Chief Warden etc.# Core Teaching Courses are: VLSI Physical design, Digital Systems, IC Technology, CAD for VLSI, CMOS Digital Design, VHDL & FPGA designs, Microprocessor/Microcontrollers & Embedded Systems.# Academic Experience:Introducing new programs at UG/PG levels, designing/modifying the course curriculum for B.Tech/M.Tech/PhD programs, Research & Developments and Handling the Funded Projects, Conducting Conferences/Seminars/Workshops/FDPs etc.# Administration: Director IQAC, Heading the department, NEP-2020 Implementation, NAAC/NBA Accreditations, Development of new labs & Conducting Examination at university level.# Certifications- VLSI Physical Design from Chip Edge Banglore - SWAYAM NPTEL Courses- CMOS Digital Design - Digital Electronics & - VLSI Design Flow: RTL to GDS# Hands-on experience/Skill over the VLSI Design tools- Proficiency in Synopsys DC, ICC2, PD & ASIC flow- RTL to GDSII complete flow at block level design @ 14nm technology node- Sanity Check, Floorplanning, Power Planning, Placement, CTS, Routing & Timing analysis- Pre-layout and Post-layout STA- Proficiency in FPGA architectures for Video/Image processing- Xilinx (ISE, EDK & Plan Ahead), Modelsim, etc- Experience and good knowledge of VHDL & Verilog- FPGA\'s RCS architectures- Experience in LINUX & TCL

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Manoj Pandey — Associate Professor (Ece) & Dy Controller of Examinations at Sarala Birla University - Sbu, Ranchi in Ranchi, JH, IN | Unifers