M. Sultan M. Siddiqui

About M. Sultan M. Siddiqui

I have Industrial and Academic Experience in the field of memory circuit design. I had worked through various Planar CMOS technology nodes: 180nm, 130nm, 90nm, 65nm, 28nm, 22nm and 20nm; FinFET CMOS technology nodes: 16nm, 12nm, 14nm, 7nm, 5nm, 4nm and 3nm; FDSOI CMOS technology nodes: 28nm and 22nm; and BCD (Bipolar-CMOS-DMOS) technology nodes: 130nm and 180nm. I have expertise in the following domains:• Single & Dual port SRAMs, Register Files, ROM and TCAMs.• Memory architecture trade-offs: performance, area and power consumption.• Memory bit cell characterization, RMs/WMs and Sense amplifier analysis.• Parasitic modeling of critical paths and Read & Write assist.• Memory cluster verification to assist in memory compiler design validation.• Development of netlister tiler for memory compiler simulations (Hi-Z, ERC checks and DC Power checks).• Development of kfactor, caps and slew measurements for memory compilers.• Timing, Power, Leakage and LVF characterization for memory compiler.• Memory compiler design marginalities: Logic margins, Power margins & BIST margins.• Hold and Setup marginalities using SYNOPSYS NANOTIME.• ASV (Address Scramble Verification) and SDV (Strap Distribution Verification) for memory compiler.• VCS (Functional verification) and ESP-CV for memory verification & seq. equivalent checking.• ESP-CKT (Circuit Verification) and ESP-PIV (Power Integrity Verification) for memory.• CADENCE SPECTRE, SYNOPSYS HSPICE, HSIM, FINESIM and XA simulators.• Cadence Virtuoso Custom IC Design Tools and Assura Verification Tools.• Mentor Graphics Calibre Verification Tool.• Leaf cells layout reviews and EMIR.• Automation skills through script files employing PERL, TCL and C/C++.• Active-HDL, FPGA Express and ModelSim-ALTERA.• Coding through MATLAB.I am serving as a • reviewer for Transactions on Circuits and Systems I (TCAS I) and II (TCAS II).• reviewer for Transactions on VLSI Systems (TVLSI).• reviewer for ISCAS conference.• member of Board of Studies (BoS) in Manipur, India.• member of Board of Studies (BoS) in NIT Arunachal Pradesh, India.

Experience

1. Sr Manager, R & d Engineering

   Synopsys Inc

   Feb 2025 — Present · Noida, IN

   Low power and High speed Memories

Education

• Indian Institute of Technology, Delhi

  Doctor of Philosophy (Ph.D.), Neurocomputing and VLSI circuit design

• Dawn High School

  High School, SSC

  1989 — 1994

• Bangalore University

  Bachelor's Degree, ECE

  1997 — 2001

• Jawaharlal Nehru Technological University

  M.Tech, Digital System & Computer Electronics

  2002 — 2004

• Sultan-Ul-Uloom Junior College

  10+2, MPC

  1994 — 1996

Skills

• Soc
• Cadence Virtuoso
• C
• Ternary Content Addressable Memory Design
• Vlsi
• System on a Chip (Soc)
• Cmos
• Application-Specific Integrated Circuits (Asic)
• Field-Programmable Gate Arrays (Fpga)
• Memory Test
• Memory Built in Self Test
• Memory Design
• Embedded Systems
• Eda
• Static Timing Analysis
• Rtl Design
• Matlab
• Functional Verification
• Very-Large-Scale Integration (Vlsi)
• Fpga
• Analog Circuit Design
• Verilog
• Asic
• Semiconductors
• C++
• Integrated Circuit Design
• Tcl
• Circuit Design
• Spice
• Vhdl
• Simulations