Gopalakrishnan Sundararajan

About Gopalakrishnan Sundararajan

As an EDA Tools Software Engineer at Intel Corporation, I have 6+ years of experience in backend physical design, tools, flows, and methodologies (TFM). I am responsible for enabling tools and features for Intel IP and SOC products, maintaining and supporting the integration flows, and developing validation mechanisms for the collaterals. I also collaborate with EDA tool vendors to pioneer new features and solutions for Intel designs.Prior to my current role, I was a Physical Design Engineer at Intel PSG group, where I contributed to two key tapeouts in timing, RV, and power functions. I have extensive hands-on experience in block level and full chip level integration, timing analysis and convergence, and SDC constraints validation using Synopsys tools. Additionally, I have a strong research background in LDPC decoding algorithms, fault and process tolerant circuit design, and error correction, with 10+ patents/papers/book chapter and 150+ citations in and conferences. I am an EB-1B and EB2-NIW recipient, and an O1-A visa holder, recognized for my outstanding research and contributions to the field of electrical and computer engineering.

Experience

1. Senior Member of Technical Staff

   Cerebras

   Jun 2024 — Present · Austin, TX, US

   Block owner for a small PNR block, Timing correlation between ICC2/FC and PT. Enabling MIS in PT flows. Enabling Primeclosure ECO flows for Wafer Scale Engine (WSE).

Education

• Oklahoma State University

  Master's Degree, Electrical and Computer Engineering

  2007 — 2010

• ANNA UNIVERSITY - India

  Bachelor's Degree, Electronics and Communications Engineering

  2001 — 2005

• Utah State University

  Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering