Abhishek Bhattacharjee

About Abhishek Bhattacharjee

I am doing a full-time Ph.D.(M.Tech + 2) from NIT Agartala in the area of Low Power VLSI and Reliability of Transistors. I have a good understanding of memory designs. I have worked on the SRAM cell and proposed a methodology to reduce the NBTI effect and improve the reliability of the SRAM cells. The simulations are done on Cadence Virtuoso (RelXpert) using UMC 28 nm technology library. And using the proposed approach, the reliability of the SRAM cell improves significantly. Apart from the SRAM cells, I have worked on power gating circuits. Moreover, I have proposed a methodology to co-optimize the NBTI effect and leakage power. All of my research works are published in different reputed SCI-indexed international Journals. I have done M. Tech in VLSI design from Heritage Institute of Technology in 2017. I am looking for an opportunity in the field of Memory design/ Analog design.

Experience

1. Design Engineer Ii

   Cadence

   Aug 2025 — Present · Bangalore Urban, IN

Education

• Tripura Institute of Technology

  Bachelor of Engineering (BE), etce

  2011 — 2015

• National Institute of Technology Agartala

  Doctor of Philosophy - PhD, VLSI

• Heritage Institute of Technology

  M.Tech, VLSI